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Leading Zero Anticipator (LZA) is a technique to calculate the number of leading zeros of the result in parallel with the addition. General algorithms can work effectively for a subtraction, and obtain the leading one position from exponents of operands for an addition or a multiply-add-fused (MAF) operation. However, using exponents to get leading zero number can introduce another error of one bit because of a carry into the leading one position. Moreover, when taking denormalized operands into account, the leading one position does not relate with exponents anymore. This paper presents a novel concurrent error detection circuit for an exact LZA which can work effectively for both addition and subtraction. In addition, a simpler pre-encoding method is employed to reduce the hardware complexity of the concurrent error detection circuit. The total area of the proposed LZA is reduced by 7.5% compared with that of a general LZA.