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As technology scales, interconnection has played an important role in improving performance and reducing power consumption of CMP. While most of studies are mainly focus on two-dimension (2D) interconnection. With the increase of cores, the traditional 2D network techniques are no longer efficient for many-core processors. Three-dimension (3D) interconnection appears as a promising solution in high performance and power efficient interconnects design. In this paper, we propose a low-diameter 3D interconnection network for many-core processors. In our network, long range links are used to replace multiple short links. The path between any two nodes is no more than 5 hops. All the designs are evaluated by using a cycle-accurate 3D network simulator, and integrated with the Orion power model for performance and power analysis. The results show up to 33.00% latency reduction and 24.39% energy reduction on average compared with canonical 3D mesh network.
Computer Engineering and Technology (ICCET), 2010 2nd International Conference on (Volume:1 )
Date of Conference: 16-18 April 2010