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New tendencies envisage multi-core as a promising solution for real-time application. And the key challenge is how to improve the communication efficiency. In this paper, we propose a new multi-core architecture, which adopts the hybrid interconnection composed of both bus-based and NoC architecture, and we also introduce several technologies to improve its communication efficiency. Adopting the new architecture, we design a multi-core prototype chip which integrates 12 ARM compatible cores. Further, we design a real-time fade-in-fade-out video demo system base on the prototype chip and evaluate the communication performance. The hybrid multi-core prototype chip runs at 90 MHZ, and can accomplish real-time fade-in-fade-out processing of 4 lane video (320×240, 30 fps).
Computer Engineering and Technology (ICCET), 2010 2nd International Conference on (Volume:1 )
Date of Conference: 16-18 April 2010