By Topic

Prototype design of hybrid multi-core architecture for real-time application

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Ning Hou ; Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China ; Duoli Zhang ; Gaoming Du ; Li Li
more authors

New tendencies envisage multi-core as a promising solution for real-time application. And the key challenge is how to improve the communication efficiency. In this paper, we propose a new multi-core architecture, which adopts the hybrid interconnection composed of both bus-based and NoC architecture, and we also introduce several technologies to improve its communication efficiency. Adopting the new architecture, we design a multi-core prototype chip which integrates 12 ARM compatible cores. Further, we design a real-time fade-in-fade-out video demo system base on the prototype chip and evaluate the communication performance. The hybrid multi-core prototype chip runs at 90 MHZ, and can accomplish real-time fade-in-fade-out processing of 4 lane video (320×240, 30 fps).

Published in:

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on  (Volume:1 )

Date of Conference:

16-18 April 2010