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Enhancing the performance and fairness of shared DRAM systems with sharing-aware scheduling

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3 Author(s)
De-Li Wang ; Coll. of Comput. Sci., Northwestern Polytech. Univ., Xi''an, China ; De-Yuan Gao ; Dang-Hui Wang

CMP (chip multiprocessor) is simply getting more ubiquitous these days. Most of the processors used in servers, desktop and even in embedded applications are featuring several cores. And it is predicted that chips with many more cores will become widespread in the near future. As cores on the same chip share the DRAM memory system, multiple threads executing simultaneously will interfere with each other's memory requests. While recent studies have focused a lot on the multi-programmed applications, less work is done in the single multi-threaded domain. In this paper, we examine polices for managing the fairness of off-chip memory bandwidth among different threads in parallel applications. First, we show that there are also fairness problems existing between different threads from the same parallel program. Then we find one cause to this is that the shared data memory accesses are not explicitly classified. Based on this observation, we propose a sharing-aware DRAM scheduler design that provides fair service to different threads in parallel programs. Experimental results show that this scheme can effectively improve the fairness among different threads and also improve the performance of whole system.

Published in:

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on  (Volume:6 )

Date of Conference:

16-18 April 2010

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