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Low-power design is quite necessary for the modern power-sensitive embedded systems. Translation Look-aside Buffers (TLBs) can take up significant on-chip energy while translating page addresses. In this paper, we study the memory access behavior of applications drawn from SPEC benchmark suits. In such study, we define a parameter, page interval, to direct our research on saving the power dissipation of dTLB. After that, we present an optimized low-power design for dTLB by introducing an Access Recording Buffer (ARB). The ARB specifically records the high-order bits of the recently-used logical address and that of the corresponding physical address. To decide the optimal configuration of the ARB, we further study different depths and replacement policies to observe their effects on system performance and energy consumption. By running applications drawn from SPEC benchmark suits, the experiment shows most page address translation can be done in the ARB, thus significantly reducing the need to look up the dTLB. Our experiments show that using the ARB can yield an average on-chip energy saving of 30% for dTLB.