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Functional verification of external memory interface IP core based on restricted random testbench

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3 Author(s)
Qingdong Meng ; Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China ; Zhaolin Li ; Fang Wang

The design of SoC system, random test is becoming an application for IP cores verification gradually. In order to test the integrated EMIF IP core, the restricted random verification method is used with added flexible generation of parameterized script files and adaptable random test points. Based on the verification environment built, some tasks were created and passed as transactions according to the analysis of simulation interface and output results. Standard memory modules were integrated with timing factors to support verification. Comparing with the direct verification, the method present in this paper is much more flexible and practicable, and can improve the whole efficiency of verification.

Published in:

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on  (Volume:7 )

Date of Conference:

16-18 April 2010