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This paper presents design techniques of a multiphase clock generator using a low-jitter delay-locked loop (DLL) or its array for the developments of high-resolution multi-channel time-to-digital converters (TDCs). The low-jitter technologies for both a single DLL and an array of DLL are discussed. Based on the previous work on the design of a single DLL with 32 delay cells, an array of mixed-mode low-jitter DLLs is proposed for achieving smaller time taps. The array of DLL is successfully designed and embedded into a prototype chip of a three-channel high-resolution TDC in 0.35 CMOS process. The operational range of the DLL in the array is from 50 MHz to 120 MHz. The RMS value of measured cycle-to-cycle jitter in the DLL is about 7 ps while the peak-to-peak value is about 20 ps. A bin size of 71 ps can be achieved by using a reference clock of 100 MHz. The DNL and INL of the evaluated chip are 0.58 LSB and 0.63 LSB, respectively. The static power dissipation of the DLL array is about 23 mW.
Date of Publication: June 2010