HF performance characterization and prediction of 2D redistribution layer interconnects in a 3D-integrated circuit stack

Effects due to 3D level stack on HF propagation performance of 2D interconnects integrated in the Back End Of Line (BEOL) or realized on the back face of a reported silicon substrate are investigated. The impact of silicon substrate on propagation exponents and delays is pointed out for 2D interconnects used as redistribution lines between stacked chips. In a first part, HF simulation and measurement results are compared to validate electrical models of interconnects. In the second part, a parametric study is performed in order to predict and optimize performances of 2D interconnects for different processes of 3D stacking.