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A Management Strategy for the Reliability and Performance Improvement of MLC-Based Flash-Memory Storage Systems

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2 Author(s)
Yuan-Hao Chang ; Dept. of Electron. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan ; Tei-Wei Kuo

Cost has been a major driving force in the development of the flash-memory technology. Because of this, serious challenges are now faced for future products on reliability and performance requirements. In this work, we propose a management strategy to resolve the reliability and performance problems of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of advanced multilevel cell flash-memory chips. The capability of the proposed approach is analyzed with reliability considerations and evaluated by experiments over realistic workloads with respect to the reliability and performance improvement.

Published in:

Computers, IEEE Transactions on  (Volume:60 ,  Issue: 3 )

Date of Publication:

March 2011

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