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Gated Diode Investigation of Bias Temperature Instability in High- \kappa FinFETs

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9 Author(s)

Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n+/p- /p+ structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be NIT ≅ 1011 cm-2 for SiO2/2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of ΔNIT(t) under negative bias stress conditions (NBTI) suggests NIT is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.

Published in:

Electron Device Letters, IEEE  (Volume:31 ,  Issue: 7 )

Date of Publication:

July 2010

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