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Browse Journals & Magazines > Electron Device Letters, IEEE ...> Volume:31 Issue:7 Help

Gated Diode Investigation of Bias Temperature Instability in High- \kappa FinFETs

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9 Author(s)
Young, Chadwin D. ; SEMATECH, Albany, NY, USA ; Neugroschel, Arnost ; Matthews, K. ; Smith, C.
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Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n+/p- /p+ structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be NIT ≅ 1011 cm-2 for SiO2/2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of ΔNIT(t) under negative bias stress conditions (NBTI) suggests NIT is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.

Published in:
Electron Device Letters, IEEE  (Volume:31 ,  Issue: 7 )

Date of Publication: July 2010

Page(s):
653 - 655
ISSN :
0741-3106
INSPEC Accession Number:
11375544
Digital Object Identifier :
10.1109/LED.2010.2049635
Product Type:
Journals & Magazines
Date of Publication :
10 June 2010
Date of Current Version :
24 June 2010
Issue Date :
July 2010
Sponsored by :
IEEE Electron Devices Society

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