Gated Diode Investigation of Bias Temperature Instability in High- $\kappa$ FinFETs

Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n
⁺
/p
^-
/p
⁺
structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be N
_IT
≅ 10
¹¹
cm
^-2
for SiO
₂
/2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of ΔN
_IT
(t) under negative bias stress conditions (NBTI) suggests N
_IT
is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.