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H.264/AVC is the latest video coding standard. It reaches the highest compression rates when compared to previous standards. On the other hand, it has a high computational complexity mainly due to motion estimation and its mode decision. Considering the high number of calculations, hardware implementations become essential. Moreover, it is important try to find alternatives to simplify the H.264/AVC mode decision. Another desirable improvement is an efficient way to provide the residual blocks of motion estimation to the next encoding steps. Addressing hardware architectures, this work presents an architecture for fast inter mode decision and production of residual blocks. The variable block-size motion estimation architecture used is based on full search algorithm, SAD calculation, and it produces the 41 motion vectors within a macroblock. The architectures were described in VHDL and mapped to a Xilinx FPGA. Considering the results, the architecture reaches real time for HDTV 720p at 41 fps.
Programmable Logic Conference (SPL), 2010 VI Southern
Date of Conference: 24-26 March 2010