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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

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7 Author(s)
Yan Zhu ; Analog and Mixed Signal VLSI Laboratory and Faculty of Science and Technology, University of Macau, Macao, China ; Chi-Hang Chan ; U-Fat Chio ; Sai-Weng Sin
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A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:45 ,  Issue: 6 )