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Rewiring is a useful technique that perturbs the logic of Look-Up Tables (LUTs) without changing the functions of circuits. This internal logic perturbation can be used to trade for critical LUT-external logic/wire removals for EDA improvements. In this paper, we design a flow of embedding the rewiring engine into routing process for FPGA improvement. In our design, we change the priorities of target wires according to their net delays for the purpose of acquiring the best delay reduction. Then we use our evaluation function to expand the choices of alternative wires. We also design a method to choose the pins of Configurable Logic Blocks (CLBs) which have more than one unused pins. We use VPR as our place-and-route tool. Compared with the high quality results of VPR, our method can reduce the critical path delay up to 8.6%. These encouraging results suggest that the optimization domain of FPGA flow still has much room to explore and rewiring technique will be a simple and powerful choice.