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Multi-processor based CRC computation scheme for high-speed wireless LAN design

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4 Author(s)
Yoon, S.-R. ; Dept. of Inf. & Commun., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Seo, S. ; Huang, M.L. ; Park, S.-C.

Presented is a software cyclic redundancy check (CRC) parallel computation scheme for the realisation of a high-speed wireless communication system on a multi-processor design platform. The proposed CRC generation scheme was applied to the IEEE 802.11n WLAN system. As a result, the proposed CRC scheme is capable of meeting tight latency constraint to achieve 144 Mbit/s throughput at a processor frequency less than 200 MHz, when evaluated with register-transfer-level simulation.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 11 )