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Design of high speed high SNR bit-stream adder based on ΣΔmodulation

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4 Author(s)
Liang, Y. ; Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China ; Wang, Z.G. ; Meng, Q. ; Guo, X.D.

A bit-stream adder circuit based on sigma delta (ΣΔ) modulation is proposed and designed in the TSMC 0.18 μm CMOS process. The operating frequency and signal-to-noise ratio (SNR) performance were verified through simulation in Hspice and Matlab. The simulation results show that the proposed circuit can work at a frequency of higher than 10 GHz. Compared with conventional bit-stream adder circuits, the proposed circuit can achieve much better SNR performance or the same SNR performance with several times higher operating frequency and about 20% hardware saving.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 11 )