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FPGA-based architecture of a DS-UWB Channel Estimator and RAKE Receiver employing a hybrid selection scheme

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2 Author(s)
Thomos, C. ; Dept. of Electr. & Comput. Eng., Univ. of Patras, Patras, Greece ; Kalivas, G.

A low-complexity architecture of a RAKE Receiver subsystem for a Direct Sequence Ultra-Wideband (DS-UWB) is presented, followed by FPGA implementation and system performance results. The proposed subsystem is composed of a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) maximal ratio combining (MRC) RAKE Receiver (RR), which combines the benefits of both partial and selective RAKE receiver algorithms. The implementation of the HPS component is based on a parallel selection structure that picks the strongest multipath rays of the channel impulse response. Our work is focused on a highly parallel, modular design based on FPGA technology and optimized for high performance. The obtained results demonstrate the tradeoff between energy capture, performance and receiver complexity.

Published in:

Telecommunications (ICT), 2010 IEEE 17th International Conference on

Date of Conference:

4-7 April 2010