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Implementation of embedded systems-on-chip on modern field programmable gate arrays (FPGAs) chip is doable due to its large density. Architecture of multilevel computing focusing on its embedded processor is suggested in our project. The architecture design of embedded processor presents the challenges and opportunities that stem from the task coarse granularity and the large number of input and output for each task. Thus, we have designed a new architecture called Embedded Concurrent Computing (ECC). The entire embedded processor architecture is implemented on the FPGA chip using VHDL. We have synthesized and evaluated the embedded system based on an Altera environment by using a DE2 board. The performances of a realistic application show scalable speedups comparable to that of the simulation. Furthermore, the results show the accuracy of Extended Kalman Filter (EKF) rather than the Kalman Filter (KF) in identifying the landmarks and target in underwater environment, and the usefulness of the multiple filtering techniques when the nonlinearities are too large due to linearization errors. We believe that implementation has been achieved in providing low complexity in terms of FPGA resource usage and frequency. In addition, the design methodology allows the embedded processor to be scalable as the entire system grows.
Date of Conference: 18-19 Nov. 2009