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A 2-MHz bandwidth Δ-Σ fractional-N synthesizer based on a fractional frequency divider with digital spur suppression

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2 Author(s)
Pin-En Su ; Dept. of Electr. Eng., UCLA, Los Angeles, CA, USA ; Pamarti, S.

A 2-MHz delta-sigma fractional-N frequency synthesizer based on a staggered switching fractional frequency divider is presented in this paper. The phase generator based fractional frequency divider provides lower instantaneous phase error and hence lowers the delta-sigma quantization noise, so that the synthesizer loop bandwidth can be increased. To suppress fractional spurs due to phase generator phase errors, a digital spurious tone suppression technique is adopted. The frequency synthesizer is implemented in 0.18-μm CMOS process, and it operates at 2.1-GHz carrier frequency with 2-MHz bandwidth. Excluding the output buffer, the synthesizer consumes 33.9-mA and is capable of transmitting 4-Mb/s GFSK signal.

Published in:

Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE

Date of Conference:

23-25 May 2010

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