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In this paper, we present a cost-effective JFET integrated in 0.18μm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics, this JFET device also demonstrates promising RF characteristics such as maximum frequency, linearity, power handling capability, power-added efficiency, indicating a good candidate for RF designs.