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Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

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2 Author(s)
Gill, G. ; Univ. of North Carolina at Chapel Hill, Chapel Hill, NC, USA ; Singh, M.

This paper presents a systematic approach for microarchitectural exploration in pipelined asynchronous systems, with the goal of achieving a specified throughput target while minimizing a given cost function (based on energy, area, etc.). The method includes a general framework that (i) allows for a rich extensible set of microarchitectural transformations for improving throughput; and (ii) can handle a variety of cost functions, such as area, energy, Eτ2 and the energy-area product.In general, the space of transformations that can be applied to a given circuit is potentially infinite because an arbitrarily long sequence of transformations may be applicable. To compound the challenge, the value of the given cost function can change non-monotonically as successive transformations are applied (e.g., some transformations increase area, while others decrease area), thereby making it difficult to apply a typical branch-and-bound approach to prune the search space. Our method employs simple but effective heuristic search strategies (including greedy, look ahead, and breadth-first). A key contribution is to identify commutativity of certain transformations, thereby pruning the design space significantly. The approach was automated and applied to a number of examples. Various throughput targets were assumed: from 50% to 20x throughput improvement. In each example, the approach was successful in meeting the throughput target.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on

Date of Conference:

3-6 May 2010