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Parallel architecture dedicated to connected component analysis

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4 Author(s)
E. Mozef ; Lab. d'Instrum. Electron., Nancy I Univ., France ; S. Weber ; J. Jaber ; E. Tisserand

This paper presents the design of a dedicated parallel architecture for connected component analysis. Categorized in one-dimensional array processors, for an image of n×n pixels, the proposed architecture has n-1 linear processing elements (PEs), n2 CAM memory modules, and a tree structure of (n/2)-1 switches allowing communication through the global bus in O(log n) unit of propagation time. Well suited for low and intermediate-level vision, this architecture allows sequential processing through its line structure which is perfectly adapted to real time image analysis from any interlaced-mode video signal. This paper presents the algorithms for connected component labeling, area and perimeter determination, all of which are in O(n log n). The performance of the proposed architecture is compared with another architecture types. The simulation results, the possibility of implementation, and future work are discussed

Published in:

Pattern Recognition, 1996., Proceedings of the 13th International Conference on  (Volume:4 )

Date of Conference:

25-29 Aug 1996