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A dynamic frequency linear array processor for image processing

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3 Author(s)
N. Ranganathan ; Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA ; N. Bhavanishankar ; N. Vijaykrishnan

In this paper, we propose a dynamic frequency linear array processor, DFLAP, for real-time image processing applications. The architecture uses a novel concept of dynamic frequency clocking which allows the chip to operate between, a maximum frequency of 400 MHz and a minimum frequency of 50 MHz based on the operation being performed. The dynamic clocking scheme is especially useful in the contest of image processing applications where certain tasks require only logic functions while others require only additions and certain others multiplication or division. The proposed architecture provides speedup by supporting two levels of parallelism and using variable frequency single clock cycle operations. DFLAP provides parallelism at the array level using multiple processing elements (PEs) and at a functional level allowing concurrent use of various units in the PE. The array architecture contains N PEs, where the image size is N×N and each PE in turn contains an a-bit arithmetic/logic unit, an 8×8 single-cycle multiplier, a shifter, a neighbor communication unit, a 32×8 dual port SRAM and a dynamic clocking unit (DCU). The DCU an each PE enables dynamic switching of clock frequencies. The dynamic clocking scheme provided a speedup ranging from 1.5 to 3 over the uni-frequency clocking for various low level pattern recognition and image processing algorithms that were mapped onto the chip

Published in:

Pattern Recognition, 1996., Proceedings of the 13th International Conference on  (Volume:4 )

Date of Conference:

25-29 Aug 1996