By Topic

A VLSI system architecture for lossless image compression

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Aruru, S.B. ; Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA ; Ranganathan, N. ; Namuduri, K.R.

This paper describes a VLSI architecture for lossless image compression based on the variable block size segmentation (VBSS) scheme. The VBSS scheme segments the image into variable size blocks, extracts the redundancy features in them, and encodes the blocks using suitable coding techniques in order to obtain maximum compression. The scheme is computationally intensive and time consuming when implemented in software. The proposed architecture fully utilizes the principles of parallelism and pipelining in order to obtain high speed and throughput. It requires simple basic cells and regular nearest-neighbor communication making it suitable for VLSI implementation

Published in:

Pattern Recognition, 1996., Proceedings of the 13th International Conference on  (Volume:4 )

Date of Conference:

25-29 Aug 1996