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Design and implementation of a low-complexity RAKE receiver and Channel Estimator for DS-UWB

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3 Author(s)
Thomos, C. ; Dept. of Electr. & Comput. Eng., Univ. of Patras, Patras, Greece ; Papadopoulos, C. ; Kalivas, G.

In this paper, the design and implementation of a low complexity Direct Sequence Ultra-Wideband (DS-UWB) receiver subsystem which incorporates a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) RAKE Receiver (RR) using maximal ratio combining (MRC) is presented. The proposed architecture demonstrates the tradeoff between energy capture, performance and receiver complexity by combining the benefits of both partial and selective RAKE receiver algorithms. We focus our work on a highly parallel, modular, synthesizable design which is based on FPGA technology and it is optimized for high performance.

Published in:

MELECON 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference

Date of Conference:

26-28 April 2010

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