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An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications

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3 Author(s)
N. Yamashita ; NEC Corp., Kawasaki, Japan ; Y. Fujita ; S. Okazaki

A newly developed one-board real-time image processing system with 10.24-GIPS peak performance is described. Such performance is possible due to a linear processor array of 256 SIMD processing elements. The IMAP-VISION chip, which is a key device of the system, integrates 32 8-bit processing elements and 32 l-Kbyte/PE memories. It also has a synchronous DRAM (SDRAM) interface with 160-MB/s bandwidth which enables a large capacity memory to be used for real-time vision applications. As the chip is designed to be able to overlap data transfer between the on-chip memories and the SDRAMs with computations, the system is capable of executing complicated algorithms flexibly without memory access overhead or shortage of memory capacity. In addition, a bit-pack function is used to improve binary image processing performance. The efficiency of this function is illustrated by a region labeling algorithm which is often used in object recognition. The system manages to process real-time region labeling and Hough transform, and shows high performance for most low-level image processing tasks

Published in:

Pattern Recognition, 1996., Proceedings of the 13th International Conference on  (Volume:4 )

Date of Conference:

25-29 Aug 1996