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Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

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6 Author(s)
M. Hiraki ; Central Res. Lab., Hitachi Ltd., Tokyo ; R. S. Bajwa ; H. Kojima ; D. J. Gorny
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This paper presents a new pipeline structure that dramatically reduces the power consumption of multimedia processors by using the commonly observed characteristic that most of the execution cycles of signal processing programs are used for loop executions. In our pipeline, the signals obtained by decoding the instructions included in a loop are temporarily stored in a small-capacity RAM that we call decoded instruction buffer (DIB), and are reused at every cycle of the loop iterations. The power saving is achieved by stopping the instruction fetch and decode stages of the processor during the loop execution except its first iteration. The result of our power analysis shows that about 40% power saving can be achieved when our pipeline structure is incorporated into a digital signal processor or RISC processor. The area of the DIB is estimated to be about 0.7 mm2 assuming triple-metal 0.5 μm CMOS technology

Published in:

Low Power Electronics and Design, 1996., International Symposium on

Date of Conference:

12-14 Aug 1996