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A 1300-V 0.34- \Omega \cdot\hbox {cm}^{2} Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers

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2 Author(s)
Elahipanah, H. ; Dept. of Electr. Eng., Semnan Univ., Semnan, Iran ; Orouji, A.A.

In this paper, for the first time, a novel power partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor is proposed with dual p- and n- charge accumulation (CA) layers near the source and the drain (DCAL-PSOI). Two new high electric field peaks are introduced by the two p- and n- CA layers in the proposed structure. Hence, a more uniform electric field is obtained due to modulation of the electric field in the drift region by the charges located in the p- and n- CA layers and buried oxide surface. Therefore, the vertical breakdown voltage (BV) is significantly improved by reducing the high bulk electric field around the source and drain regions. The influences of the proposed structure parameters on device characteristics are analyzed. For the DCAL-PSOI LDMOS with a 120-μm drift region length, the maximum BV of 1317 V is obtained by the simulation, while at the same drift region length, the maximum BVs of the conventional PSOI (C-PSOI) and conventional silicon-on-insulator (C-SOI) devices are 628 and 330 V, respectively. Moreover, the device exhibits a superior specific on-resistance (Ron, sp) of 0.34 Ω·cm2, which shows that the on-resistance of the optimized DCAL-PSOI are decreased by 91%-95% in comparison to the C-PSOI. The superior BV and Ron, sp yield to a power figure of merit (BV2/Ron, sp) of 5.1 MW/cm2. Also, the Si window alleviates the self-heating effect, and the maximum temperature of the proposed structure reduces as compared with the C-PSOI and C-SOI devices.

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Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 8 )