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In this paper, we study the operation mode and the scalability of the second generation (type II) of double-gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state “1,” whereas the total retention time is limited by the leakage associated with state “0” due to band-to-band tunneling (BTBT) at the source/drain to bulk junctions. Extensive and careful scaling analysis shows that longitudinal scaling is limited by short-channel effects related to source/drain to bulk barrier lowering, whereas transverse scaling is limited by BTBT. We conclude that type-II 1T-DRAM is somewhat more scalable than type-I 1T-DRAM (i.e., 15 nm versus 25 nm). The better scaling perspective of type-II 1T-DRAM cells is ascribed to the higher READ sensitivity, programming window, and retention time.