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In this paper, we show that the impact of process variations on the parametric measurements of semiconductor circuits can be modeled using multivariate statistical techniques. We show that it is possible to devise data transformation methods to model different kinds of measurements such as timing and leakage using multivariate statistical analysis. We use these models to propose new semiconductor spatial estimation and variability decomposition techniques. We demonstrate a new semiconductor spatial estimation technique based on the expectation-maximization algorithm. Our technique can be used to fill in the expected values of measurements at wafer locations that have been skipped or missed during parametric testing. Furthermore, we use our proposed spatial estimation method together with nested analysis of variance techniques to arrive to an accurate variability decomposition method. We extensively verify our models and results with timing and leakage variability data measurements collected from a large volume of manufactured wafers at 65 nm SOI process. Using this data we explore and quantify the trade-off between the accuracy of estimations and the reductions in the number of required parametric measurements. We demonstrate the superiority of the proposed technique for spatial estimation in comparison to geostatistical Kriging-based estimators and traditional cubic B-spline-based interpolation methods. We also show the impact of wafer sampling techniques on the accuracy of spatial estimation, and we reveal the spatial structure of various variability sources.
Date of Publication: Aug. 2010