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In this brief, a low-cost very large scale integration (VLSI) architecture is designed for multistandard inverse transform. The proposed architecture is used in multistandard decoder of MPEG-2, MPEG-4 ASP, H.264/AVC and VC-1. Two circuit share strategies, factor share (FS) and adder share (AS), are applied to the inverse transform architecture for saving its circuit resource. It is shown that the proposed multistandard inverse transform architecture can support the real-time decoding of 1920 × 1080@60 Hz high-definition video at the cost of low circuit resource.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:57 , Issue: 7 )
Date of Publication: July 2010