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Advanced junction formation for sub-32nm logic devices

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5 Author(s)
Deshpande, S.V. ; Semicond. R&D Center, IBM, Hopewell Junction, NY, USA ; Ozcan, A. ; Wall, D. ; Eunha Kim
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This paper is meant to be a general overview of recent advances in new processes and process tooling (implant and anneal) for advanced junction formation. Also included are details of impact of novel implant processes, such as cold implant and pre-amorphization (PAI) implants on Nickel Silicide (NiSi) formation. We will also discuss subtle impacts of wafer temperature during ion implantation on channel stress retention and shallow junctions in today's advanced device nodes.

Published in:

Junction Technology (IWJT), 2010 International Workshop on

Date of Conference:

10-11 May 2010