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An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

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3 Author(s)
Chatterjee, A. ; Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA ; Nandakumar, M. ; Chen Ih-Chin

In this paper the effects of technology scaling on the fraction of active power Pa wasted as short-circuit power Ps are studied through SPICE simulations. The accuracy of SPICE is verified against experimental data. SPICE simulations show that lowering VT below 0.1 V can increase Ps/Pa significantly beyond what is expected from increased subthreshold leakage. Ps/Pa is typically higher at higher Vcc but to first order Ps/Pa is determined by signal slew rates and VT. It is shown that the input slew rate is constrained by Ps/Pa at low V T and by performance at higher VT. We show that P s increases with increasing gate sheet resistance. A simple analytical model for this effect is verified against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa<10% for sub-0.25 μm technologies

Published in:

Low Power Electronics and Design, 1996., International Symposium on

Date of Conference:

12-14 Aug 1996