An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

In this paper the effects of technology scaling on the fraction of active power P_a wasted as short-circuit power P_s are studied through SPICE simulations. The accuracy of SPICE is verified against experimental data. SPICE simulations show that lowering V_T below 0.1 V can increase P_s/P_a significantly beyond what is expected from increased subthreshold leakage. P_s/P_a is typically higher at higher V_cc but to first order P_s/P_a is determined by signal slew rates and V_T. It is shown that the input slew rate is constrained by P_s/P_a at low V _T and by performance at higher V_T. We show that P _s increases with increasing gate sheet resistance. A simple analytical model for this effect is verified against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa<10% for sub-0.25 μm technologies