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An aggressive junction design concept is proposed for further scaling of bulk planar CMOS featuring selectively epi-grown raised source/drain extensions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process and carbon co-implantation. The junction design window enlarged by introducing the RSDext enables us to elaborately control slight "intentional" diffusion through the newly developed MSA process rather than aiming complete-diffusion-less junctions. Such the "effective" ultra-shallow junctions under the RSDext realized both lower parasitic resistance and lower junction leakage by eliminating current bottleneck and implant defects while maintaining superior short-channel-effect suppression. Cluster carbon co-implanted RSDext structure, which enables high boron concentration at the silicide interface and low deep halo dosage, was also effective to reduce parasitic resistance and junction leakage. We demonstrated sub-30 nm gate length CMOSFETs with one decade reduction of junction leakage, and 10% Ion improvement for both N and PFET by adapting closely positioned silicide to the gate edge (about 5 nm).