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A Hierarchical Simulation Flow for Return-Loss Optimization of Microprocessor Package Vertical Interconnects

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3 Author(s)
Arun V. Sathanur ; Applied Computational Engineering Lab., Department of Electrical Engineering, University of Washington, Seattle ; Vikram Jandhyala ; Henning Braunisch

Design of package- and board-level interconnects utilizing full-wave electromagnetic solvers, is becoming increasingly important owing to increased frequencies of operation, miniaturization, and reduced time to market. Thus, parameterization, optimization, and statistical analysis tools are becoming an invaluable part of a designer's armory. Leveraging a previously developed fast full-wave electromagnetic solver, this paper addresses the development of a framework for package interconnect design. Parametric sweeps are conducted to show the existence of optimal designs and to select the best routing strategies. Having applied the popular response surface methodology for optimization and having outlined its limitations for higher-dimensional problems, a general optimization scheme is proposed and illustrated on a differential package interconnect line. The proposed methodology features a dimensionality reduction scheme and a reusable, multidimensional look-up table preceding the global optimization phase, which is facilitated by a smooth interpolation scheme based on splines. The second phase features a custom local optimizer incorporating all the variables without any dimension reduction. This methodology has been applied to automated synthesis of a differential package line resulting in a significant improvement of the return loss performance. A statistical analysis methodology, based on utilizing the gradient, has been presented to arrive at the spread in the differential return loss, occurring due to manufacturing tolerances, around the designed response.

Published in:

IEEE Transactions on Advanced Packaging  (Volume:33 ,  Issue: 4 )