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A 10-GBd 40-Gb/s coherent optical transport is a promising technology for higher data rate communications by virtue of improved sensitivity and high spectrum efficiency. One of the major challenges in designing a 40-Gb/s coherent quadrature-phase-shift-keying receiver is to achieve high-speed data conversion at around 20-GHz sampling rate with at least 5-bit resolution. With the detailed design framework for the target requirements, this paper presents a 5-bit 20-GS/s flash analog-to-digital converter (ADC) realized in 0.18-m SiGe BiCMOS technology. The ADC includes a track-and-hold amplifier (THA) incorporated with linear distortion compensation, double-interpolation preamplifier, current bias-weighted comparator, and high-speed encoder logic. At 4 V, the THA had a bandwidth that exceeded 23 GHz and an IIP3 of 24 dBm. The ADC achieves a signal-to-noise-plus-distortion ratio of 28.6 dB and a spurious-free dynamic range of 36 dB with a 1-GHz input sinusoid sampled at 20 GS/s. The ADC has a wide resolution bandwidth of 7 GHz, and the figure of merit is 9.54 pJ/conversion-step. The ADC consumes 3.24 W from 4- and 3-V supplies when sampled at 20 GHz. The prototype ADC occupies 8.68 mm2 of silicon area.