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Low Hardware Complexity Pipelined Rank Filter

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2 Author(s)
Dragana Prokin ; Higher School of Electrical Engineering and Computer Science, University of Belgrade , Belgrade, Serbia ; Milan Prokin

The major benefit of a disclosed low-hardware-complexity pipelined rank filter is reduction in hardware complexity and increase in processing speed, due to identical pipelined stages and the absence of mask bits. Field-programmable-gate-array realization of this filter significantly reduces the number of used logic elements and registers, in comparison with the best prior art methods, and, at the same time, increases the maximum operating frequency. One rank-sample result is available at the output on each clock cycle, thus enabling real-time nonlinear image processing.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:57 ,  Issue: 6 )