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Chip stacking with through-silicon-vias (TSV) technology for 3-D packaging of electronic devices was investigated. A new process of direct solder bumping on Si wafers without photoresist (PR) mould was designed and applied in this study. The Cu extrusion process on the via was also omitted for process simplification. This simplified process can be useful for cost reduction and increased productivity. The substrate for the experiments was a p-type 〈100 〉 Si wafer of 100 mm diameter. In order to produce the vias, the Si wafer was etched by a deep reactive ion etcher (DRIE) using SF6 and C4F8 plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO2, Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm2 and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm2 and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm2. The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by micro-soldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu6Sn5 intermetallic compound was pr- - oduced with a thickness of 3.2 μm. Through this study, a process for non-PR solder bumping by electroplating and wafer stacking with TSV was achieved successfully.
Date of Publication: Nov. 2010