By Topic

A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chua-Chin Wang ; Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan ; Chia-Hao Hsu ; Szu-Chia Liao ; Yi-Cheng Liu

A fully bidirectional mixed-voltage input/output (I/O) buffer using a novel floating N-well circuit is presented. To provide appropriate gate voltages for output stage transistors, a dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon using 0.18 μm CMOS process that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 8 )