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Compiler driven architecture design space exploration for DSP workloads: A study in software programmability versus hardware acceleration

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2 Author(s)
Michael C. Brogioli ; School of Electrical and Computer Engineering, Rice University, Houston, Texas 77005, USA ; Joseph R. Cavallaro

Wireless communications and video kernels contain vast instruction and data level parallelism that can far outstrip programmable high performance DSPs. Hardware acceleration of these bottlenecks is commonly done at the cost of software flexibility. Many vendors, however, view software as intellectual property and prefer a software solution that is a proprietary implementation. The paper uses a research compiler for architectural design space exploration to present comparisons between compiler generated scalable software programmable DSP architectures versus hardware acceleration implementations. It shows that scaled up compiler generated software programmable DSP architectures can be attractive alternatives to non-programmable hardware acceleration.

Published in:

2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers

Date of Conference:

1-4 Nov. 2009