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Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate

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5 Author(s)
Jaeyong Chung ; Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA ; Joonsung Park ; Abraham, J.A. ; Eonjo Byun
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This paper presents a built-in self repair analyzer with the optimal repair rate for embedded memory arrays. The proposed method requires only a single test, even in the worst case. By performing the must-repair analysis on the fly during the test, it selectively stores fault addresses, and the final analysis to find a solution is performed on the stored fault addresses. To enumerate all possible solutions, existing techniques use depth first search using a stack and a FSM. Instead, we propose a new algorithm and its combinational circuit implementation. Since our formulation for the circuit allows us to use the parallel prefix algorithm, it can be configured in various ways to meet area and test time requirements. The total area of our infrastructure is dominated by the number of CAM entries to store the fault addresses, and it only grows quadratically with respect to the number of repair elements.

Published in:

VLSI Test Symposium (VTS), 2010 28th

Date of Conference:

19-22 April 2010