Referenced Items are not available for this document.
This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell.
Published in:
VLSI Test Symposium (VTS), 2010 28th
Date of Conference: 19-22 April 2010
- Page(s):
- 153 - 158
- ISSN :
- 1093-0167
- Print ISBN:
- 978-1-4244-6649-8
- INSPEC Accession Number:
- 11309263
- Conference Location :
- Santa Cruz, CA
- Digital Object Identifier :
- 10.1109/VTS.2010.5469588
- Product Type:
- Conference Publications
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