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CSER: BISER-based concurrent soft-error resilience

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6 Author(s)
Laung-Terng Wang ; SynTest Technol., Inc., Sunnyvale, CA, USA ; Touba, N.A. ; Zhigang Jiang ; Shianling Wu
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This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell.

Published in:

VLSI Test Symposium (VTS), 2010 28th

Date of Conference:

19-22 April 2010