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Power noise and its impact on production test and validation of SoC devices

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1 Author(s)
Karim Arabi ; Qualcomm, Inc.

Abstract form only given. Power integrity is emerging as a major challenge in deep-submicron SoC designs. The lack of accurate prediction is complicating timing closure, production test, and speed grading of high-performance SoCs. The IC industry is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. These advanced technologies pose unexpected challenges to the semiconductor industry. To reduce power dissipation, manufacturers have scaled down supply voltage in each successive technology. Designers analyzed power supply noise with static voltage drop (SVD) analysis, which might not reflect the true nature of power supply fluctuations. Dynamic voltage drop (DVD) analysis is complementing the SVD analysis. Power consumption and power supply noise will likely be the two main challenges of semiconductor design over the next few years. Here, we are concerned with maintaining the power integrity of DSM designs. Voltage drop in the power grid is due to two components: IR and Ldi/dt. R represents the resistances of the power mesh network, power pads, and device package. L represents the inductances of the power mesh network, power pads, and device package. Our goal is to provide useful information to properly manage supply noise in large SoCs. We propose and validate the use of two metrics to qualify a DVD profile and its impact on a design's timing performance. The DVDavg metric is the DVD profile's average value in the timing cycle, and DVDmax is the DVD profile's peak value in the timing cycle. These simplified metrics are design optimization indications that accelerate the design process. It is also important to correlate power supply noise estimation tools with silicon results to ensure dependable data for reducing DVD. There are many techniques for monitoring power supply noise on chip. These techniques are not suitable for production environments, because they require either significant area - - or complex off-chip data processing. To overcome these limitations, we investigated a simple monitoring technique based on undersampling. This technique eliminates the need to trade accuracy for speed or vice versa. We also focus on minimizing power noise using decaps and the new design considerations necessary as technology scales below 45 nm. Decaps hold a reservoir of charge and are placed around regions of high current demand. When large drivers switch, nearby decaps provide a source of current that reduces IR and Ldi/dt voltage drops to keep the target average and peak supply voltages within their noise budgets (DVDavg and DVDmax). An area overlooked in the past is the management of supply noise during the testing process. Scan test mode is vulnerable to power supply noise because switching activity is typically three to four times higher than in normal mode as a result of the DFT strategy. This leads to excessive voltage drop during scan testing. In some cases, voltage drop in scan mode has been so excessive that it has resulted in inadvertent logic value toggling and test result corruption. The issue is more critical for delay testing because the chip is tested at speed, and speed degradation caused by voltage drop fluctuations creates measurement noise. Performance degradation in scan mode due to power supply noise can be as much as 15%, meaning test engineers should perform delay testing at slower frequencies to ensure that good devices don't fail the test. To address this issue, we adopted a hierarchical scan flow with special treatment of the scan-enable signal. We also investigated a new multiple-launch scan test technique to reduce the DVD disparity between delay testing and functional mode.

Published in:

2010 28th VLSI Test Symposium (VTS)

Date of Conference:

19-22 April 2010