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This paper compares two realisations of a self-timed ring arithmetic operator for division and square-root extraction. The operator receives its inputs and delivers its outputs in conventional binary notations. The first circuit design uses Differential Cascode Voltage Switch Logic. The second adds True Single Phase Clock latches in the ring. It is shown that this addition both reduces the minimum number of stages demanded by self-timed rings and decreases the "cycle time", which has an influence on the optimal number of stages and on the speed of the ring. The two chips have been generated at the CNET-CNS using a proprietary self-timed standard cell library in three-metal 0.5Â¿m CMOS technology.