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A new method to calculate the soft error rate (SER) of CMOS logic circuits with dynamic pipeline registers is described and verified through soft error rate measurements of dynamic shift registers. This method also takes low power circuits into consideration. Based on this method the SER of a pipelined multiplier is calculated for a 0.6 ¿¿m, 0.3 ¿¿m and 0.12 ¿¿m technology. It has been found, that the SER of pipelined sub-¿¿m CMOS logic circuits may become too high for many applications, so that countermeasures have to be taken.