By Topic

A Standardized Method Reduces Design Time of C-MOS Integrated Circuits and Enables Automatic Checking

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
J. C Bertails ; THOMSON-CSF Division SESCOSEM 38120 SAINT - EGREVE ; J. Zirphile

A method based on a specific implantation associated with an effort of standardization allows to greatly simplify C-MOS integrated circuit design and checking. In spite of a drastic reduction in the number of the different elementary constituents used, realized circuits exhibit excellent characteristics without prohibitive increase of the chip area.

Published in:

Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European

Date of Conference:

21-24 Sept. 1976