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A Standardized Method Reduces Design Time of C-MOS Integrated Circuits and Enables Automatic Checking

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2 Author(s)
Bertails, J.C. ; Div. Sescosem, Thomson-CSF, St. Egreve, France ; Zirphile, J.

A method based on a specific implantation associated with an effort of standardization allows to greatly simplify C-MOS integrated circuit design and checking. In spite of a drastic reduction in the number of the different elementary constituents used, realized circuits exhibit excellent characteristics without prohibitive increase of the chip area.

Published in:

Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European

Date of Conference:

21-24 Sept. 1976