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A 32 kbit Variable Length Shift Register for Digital Audio Application

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2 Author(s)
Marcel Pelgrom ; Philips Research Laboratories, PO Box 80000, 5600JA Eindhoven, The Netherlands. ; Henk Termeer

On this chip dynamic shift registers are combined with high density CCD SPS memory blocks. The shift register length can be adjusted from 17 to 32767 clock periods. The chip has been realized in a 2.5 ¿n NMCS process with CCD option.

Published in:

Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European

Date of Conference:

16-18 Sept. 1986