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Hierarchical Design Verifications based upon a Topological Access to Circuit Data

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2 Author(s)
Berger, J. ; Laboratoire de Genie Informatique de l''IMAG/CNRS, BP 68 38402 St Martin d''heres cedex FRANCE ; Mazare, G.

This paper describes a method that uses design hierarchy, signal connectivity information, and topological data retrieval to perform incremental design rule checking, and electrical node extraction.

Published in:

Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European

Date of Conference:

16-18 Sept. 1986