Voltage Reduction for 4Mbit-CMOS-DRAM

Different types of voltage reduction circuits for application to VLSI-DRAMs have been investigated. A lumped element network description of the circuits and the distributed power supply of a 4Mbit chip has been developed to model the load characteristic of the memory in a realistic way. It is shown, that the peak currents in the active cycle can be delivered by the distributed capacities of the supply lines, thus the switching speed of the reduction circuit can be substantially less than the switching speed of the decoder or amplifier circuits.